1. Field of the Invention
The present invention relates to integrated circuit memory devices based on floating gate transistor technology; and more particularly to parallel read and verify operations for page mode flash memory.
2. Description of Related Art
Flash memory is a growing class of non-volatile storage integrated circuits based on floating gate transistors. The memory cells in a flash device are formed using so called floating gate transistors in which the data is stored in a cell by charging or discharging the floating gate. The floating gate is a conductive material, typically polysilicon, which is insulated from the channel of the transistor by a thin layer of oxide, or other insulating material, and insulated from the control gate of the transistor by a second layer of insulating material.
To store data in a floating gate memory cell, the floating gate is charged or discharged using a Fowler-Nordheim tunneling mechanism, or hot electron injection mechanism. The Fowler-Nordheim tunneling mechanism is executed by establishing a large positive (or negative) voltage between the gate and source or drain of the device. This causes electrons to be injected into (or out of) the floating gate through the thin insulator. The hot electron injection mechanism is based on an avalanche process. Hot electron injection is induced by applying potentials to induce high-energy electrons in the channel of the cell, which are injected across the thin insulator into the floating gate. To induce hot electron injection, a potential is applied across the source and drain of the device, along with a positive potential on the control gate. The positive potential on the control gate tends to draw electrons from the current in the channel of the device into the floating gate.
The acts of charging and discharging the floating gate in a floating gate memory device are relatively slow compared to writing other memory types, like static or dynamic random access memory, and limit the speed with which data may be written into the device.
Another problem associated with floating gate memory devices arises because the charging and discharging of the floating gate memory devices arises because the charging and discharging of the floating gate is difficult to control over a large array of cells. Thus, some of the cells program or erase more quickly than others in the same device. In a given program or erase operation, not all the cells subject of the operations will settle with the same amount of charge stored in the floating gate. Thus, so called program verify and erase verify sequences have been developed to efficiently ensure that the memory is being accurately programmed and erased. The program and erase verify operations are based on comparing the data stored in the floating gate memory array with the intended data. The process of comparing data is relatively time consuming, involving sequencing byte by byte through the programmed or erased cells. If the failure is detected in the verify sequence, then the program or erase operation is retried. Program retries are typically executed word-by-word or byte-by-byte in prior art devices. Thus, bits successfully programmed in a byte with one failed bit are subject to the program cycle repeatedly. This can result in over-programming and failure of the cell.
One approach to resolving this issue is set forth in U.S. Pat. No. 5,163,021 by Mehrotra et al., at column 19, line 10, and referring to FIGS. 14-17.
To improve the efficiency of program and program verify operations, so-called page mode flash devices have been developed. In these devices, a page buffer is associated with the memory array. The page buffer includes a set of bit latches, one bit latch associated with each global bit line in the array. To program a page in the array, the page buffer is loaded with data to be programmed, by transferring byte by byte program data into the bit latches of the page buffer. The program operation is then executed in parallel on a bit line by bit line basis controlled by the contents of the bit latches. The verify procedure is based on clearing automatically all the bit latches in the page buffer which are successfully programmed in a parallel operation. The page buffer is then read byte-by-byte to confirm that all bits have been cleared, indicating a successful program operation.
The page mode program process is described for example in commonly owned prior PCT patent application entitled ADVANCED PROGRAM VERIFY FOR PAGE MODE FLASH MEMORY, filed Jan. 5, 1995, application Ser. No. PCT/US95/00077. In this application, the program verify operation relies on the sense amplifiers in the memory, which are limited in number, typically to 16, to sense the state of the memory cells being programmed. If the cell is programmed to the proper state, then the bit latch is reset based on the sense amplifier output. The sense amplifier is used because of charge sharing issues which arise from attempting to sense the level of bit lines in the memory array by a latch structure. The bit latch structure typically requires a significant current to reliably reset the latch. The sense amplifier circuit is able to provide sufficient current to reset the bit latch, while the bit line current through the memory cells is normally low due to the small geometry of the cells.
Other attempts at page mode program verify circuits been made. For example, Tanaka et al., "High Speed Programming and Program-Verify Methods Suitable for Low-Voltage Flash Memories," Symposium on VLSI circuits, Digest of Technical Papers, 1994, pgs. 62-64. The Tanaka et al. paper describes a system in which the bit latches are directly coupled to the bit lines of the array. However, in the design proposed by Tanaka et al., the bit latches directly fight the bit line voltage. Thus the bit line is required to conduct sufficient current to flip the bit latch. The design is therefore difficult to implement efficiently, and the data integrity is questionable because the bit line and latch fight for charge during the verify sequence.
Another prior art approach is described in Suh et al., "A 3.3V 32 Mb NAND Flash Memory With Incremental Step Pulse Programming Scheme," 1995 IEEE International Solid-State Circuits Conference, pg. 128-129 (Feb. 16, 1995). In Suh et al. a page buffer structure is described in which a current mirror structure is utilized to boost the drive capability of the bit lines for resetting bit latches. In Suh et al., a page buffer structure is described in which a current mirror structure is utilized to boost the driving capability of the bit lines for resetting bit latches. In Suh et al., during the verify operation, the wordlines are pumped to an increased voltage to double the cell current. A current mirror is coupled to with each bit line to fight with the cell. After waiting enough time for the bit line to discharge, a parallel reset of the latches is based on the resulting bit line voltage. The reliance on a current mirror in association with each bit latch requires extra current drive capability during the verify process, and increases the complexity of the circuit.
Neither Suh et al., nor Tanaka et al., describe the use of bit latches with processes which involve applying a high voltage to the bit lines, as required for some types of floating gate memory program or erase operations. Accordingly, Hung et al., U.S. Pat. No. 5,835,414 which is commonly owned by the Applicant, provides an improved page buffer which operates with low current bit lines, and is capable of supporting program, program verify, read and erase verify processes during a page mode operation. U.S. Pat. No. 5,835,414 is hereby incorporated by reference.
Another important feature to enhance the speed of such floating gate memory devices is the use of parallel bit operations. Traditionally, memory devices use sense amplifiers and connecting reference cells configured to read and verify the state of one byte of memory cells at a time. Consequently, the read and verify operations take a great deal of time to complete for a large number of memory cells in an array. To enhance access speed, sense amplifier outputs may be provided to a page buffer. To enhance speed further, more than a byte of memory cells can be read or verified in parallel by the sense amplifiers. Hollmer et al., U.S. Pat. No. 5,638,326, enables a page buffer to latch the values stored in more than a byte of memory cells in parallel without first using separate sense amplifier circuitry, while ensuring the values latched are accurate irrespective of temperature, Vcc, and process variations. As configured, each page buffer latch provides the dual function of a sense amplifier and data storage element. Such dual functionality can carry certain drawbacks including, for instance, a more complicated circuit that may sacrifice individual task efficiency for the sake of providing dual functions.
Still another prior art approach is described in Kawanara et al., "Bit-Line Clamped Sensing Multiplex and Accurate High-Voltage Generator for 0.25 um Flash Memories," ISSCC Digest of Technical Papers, pgs. 38-39, Feb. 8, 1996. A flash memory cell is described wherein each sector is programmed simultaneously by a latch circuit used for each bit-line. An associated multiplexing amplifier is then required to provide an intermittent burst transfer for each sector read. While this design uses a separate sense amplifier circuit, it should be noted that the load on the circuit might become too heavy if the phase difference between signals is too great.
Bit-by-bit precharging during the program verify operation is also desired in order to save precharge power. The prior art example of Kim et al, "A 120 mm 64 Mb NAND Flash Memory Achieving 180 ns/Byte Effective Program Speed," Symposium on VLSI Circuits, Digest of Technical Papers, pgs. 168-169, 1996, discloses a technique for full-chip burst read. During random access the bit lines are precharged. Charge sharing is also employed between the sensing node and the bit-line, wherein improved access time is achieved by using this precharging and charge sharing technique with a staggered row decoder.
What is needed in the field is an improved page buffer that operates with low current bit lines, and is capable of supporting parallel read and verify processes in a page mode. Furthermore, it is desirable that a bit-by-bit precharge be provided for program and verify operations, and that various data nodes can be isolated to avoid data conflicts.